module: dsynth_acc_with_set
parameters: double ic double setval
inputs:  double_interp clk double set double in
outputs:  double out
classes: EdgeDetect edge_clk();
static_variables: double out_sample
init: out=ic;
code:
if(set==1)
 out_sample=setval;
else if (edge_clk.inp(clk))
    out_sample=out;
out=out_sample+in;
