***** Hspice Netlist for Cell 'ofdm_overall_system_dt' *****

************** Module add2 **************
.subckt add2 in1 in2 out
.ends add2

************** Module constant **************
.subckt constant out consval=1
.ends constant

************** Module delay_fix **************
.subckt delay_fix in out delay=1.0
.ends delay_fix

************** Module divider_ideal **************
.subckt divider_ideal in div_val out
.ends divider_ideal

************** Module noise **************
.subckt noise out var=1
.ends noise

************** Module vco **************
.subckt vco vctrl squareout sineout freq=1 kvco=1
.ends vco

************** Module delay_intvector8 **************
.subckt delay_intvector8 vec_in vec_out delay=1.0
.ends delay_intvector8

************** Module delay_sample_int **************
.subckt delay_sample_int out in delay=1.0
.ends delay_sample_int

************** Module delay_vector8 **************
.subckt delay_vector8 vec_in vec_out delay=1.0
.ends delay_vector8

************** Module enable **************
.subckt enable clk_enable clk
.ends enable

************** Module int_vector8_constant **************
.subckt int_vector8_constant vec_out elem0=0 elem1=0 elem3=0 elem2=0 elem4=0 elem5=0 elem6=0 elem7=0
.ends int_vector8_constant

************** Module mux2_intvectors **************
.subckt mux2_intvectors sel vec_out vec_in0 vec_in1 vec_length=1
.ends mux2_intvectors

************** Module ofdm_add_cyclicprefix **************
.subckt ofdm_add_cyclicprefix vec_in_i vec_in_q clk_frame vec_out_i vec_out_q num_channels=1 num_cp=1
.ends ofdm_add_cyclicprefix

************** Module ofdm_ber **************
.subckt ofdm_ber bits_tx bits_rx clk_data clk_frame vec_bit_settings vec_total_bits vec_error_bits vec_error_syms vec_total_syms num_channels=1
.ends ofdm_ber

************** Module ofdm_bit_source **************
.subckt ofdm_bit_source out clk_data clk_frame vec_bit_settings
.ends ofdm_bit_source

************** Module ofdm_channel_cost259_model **************
.subckt ofdm_channel_cost259_model in_i in_q out_i out_q model=1
.ends ofdm_channel_cost259_model

************** Module ofdm_channel_estimator **************
.subckt ofdm_channel_estimator vec_in1_i vec_in1_q vec_in2_i vec_in2_q clk_frame vec_bit_settings vec_h_mag vec_h_phase vec_h_i vec_h_q num_channels=1 num_pilots=1 estimate=1
.ends ofdm_channel_estimator

************** Module ofdm_detector **************
.subckt ofdm_detector vec_dqam_i vec_dqam_q vec_bit_settings clk_frame vec_bits vec_demod_i vec_demod_q num_channels=1
.ends ofdm_detector

************** Module ofdm_fft **************
.subckt ofdm_fft vec_fft_i vec_fft_q clk_frame vec_dqam_i vec_dqam_q num_channels=1
.ends ofdm_fft

************** Module ofdm_fft_serial_to_parallel_cp **************
.subckt ofdm_fft_serial_to_parallel_cp serial_in_i serial_in_q clk_frame clk_channel vec_fft_i vec_fft_q vec_bit_settings num_channels=1 num_cp=1
.ends ofdm_fft_serial_to_parallel_cp

************** Module ofdm_frame_clk_gating_logic **************
.subckt ofdm_frame_clk_gating_logic clk_frame_in clk_frame_out
.ends ofdm_frame_clk_gating_logic

************** Module ofdm_ifft **************
.subckt ofdm_ifft vec_qam_i vec_qam_q clk_frame vec_ifft_i vec_ifft_q num_channels=1
.ends ofdm_ifft

************** Module ofdm_ifft_parallel_to_serial **************
.subckt ofdm_ifft_parallel_to_serial vec_ifft_i vec_ifft_q clk_frame clk_channel serial_out_i serial_out_q
.ends ofdm_ifft_parallel_to_serial

************** Module ofdm_impulse_generator **************
.subckt ofdm_impulse_generator clk_frame clk_channel out_i out_q in_i in_q start_sample
.ends ofdm_impulse_generator

************** Module ofdm_m_qam_generator **************
.subckt ofdm_m_qam_generator vec_bit_settings vec_bits clk_frame vec_qam_i vec_qam_q vec_bit_settings_out num_channels=1
.ends ofdm_m_qam_generator

************** Module ofdm_onetap_equalizer **************
.subckt ofdm_onetap_equalizer vec_in_i vec_in_q vec_h_i vec_h_q vec_out_i vec_out_q clk_frame vec_bit_settings num_channels=1 estimate=1
.ends ofdm_onetap_equalizer

************** Module ofdm_pilot_selector **************
.subckt ofdm_pilot_selector clk_frame sel num_pilots=0
.ends ofdm_pilot_selector

************** Module ofdm_receiver_parallel_to_serial **************
.subckt ofdm_receiver_parallel_to_serial vec_bits vec_bit_settings clk_frame clk_data out_bit num_channels=1
.ends ofdm_receiver_parallel_to_serial

************** Module ofdm_remove_cyclicprefix **************
.subckt ofdm_remove_cyclicprefix vec_out_i vec_out_q vec_in_i vec_in_q clk_frame num_channels=1 num_cp=1
.ends ofdm_remove_cyclicprefix

************** Module ofdm_transmit_serial_to_parallel **************
.subckt ofdm_transmit_serial_to_parallel in vec_out vec_bit_settings clk_frame clk_data vec_bit_settings_out num_channels=1
.ends ofdm_transmit_serial_to_parallel

************** Module ofdm_clock_generator **************
.subckt ofdm_clock_generator clk_frame clk_data clk_channel ofdm_frequency=1e6 num_cp=1 num_channels=1
xi1 n0 constant consval=0
xi0 clk_data n2 n1 divider_ideal
xi4 n1 clk_frame ofdm_frame_clk_gating_logic
xi5 clk_data n3 clk_channel divider_ideal
xi6 n3 constant consval=8
xi3 n2 constant consval=8*(num_channels+num_cp)
xi2 n0 clk_data n4 vco freq=8*(num_channels+num_cp)*(num_channels*ofdm_frequency)/(num_channels+num_cp) kvco=1
.ends ofdm_clock_generator

************** Module ofdm_transmitter_discrete **************
.subckt ofdm_transmitter_discrete vec_bit_settings x_i x_q clk_enable_tx clk_data clk_frame clk_channel bits_tx vec_qam_i vec_qam_q num_channels=1 num_cp=1.0
xi0 bits_tx clk_data clk_frame vec_bit_settings ofdm_bit_source
xi1 bits_tx vec_tx vec_bit_settings clk_frame clk_data n0 ofdm_transmit_serial_to_parallel num_channels=num_channels
xi2 vec_bit_settings vec_tx clk_frame vec_qam_i vec_qam_q n1 ofdm_m_qam_generator num_channels=num_channels
xi3 vec_qam_i vec_qam_q clk_frame vec_ifft_i vec_ifft_q ofdm_ifft num_channels=num_channels
xi4 vec_ifft_i vec_ifft_q clk_frame vec_add_cp_i vec_add_cp_q ofdm_add_cyclicprefix num_channels=num_channels num_cp=num_cp
xi6 clk_frame clk_channel x_i x_q serial_tx_i serial_tx_q n2 ofdm_impulse_generator
xi7 clk_enable_tx clk_frame enable
xi5 vec_add_cp_i vec_add_cp_q clk_frame clk_channel serial_tx_i serial_tx_q ofdm_ifft_parallel_to_serial
.ends ofdm_transmitter_discrete

************** Module ofdm_receiver_discrete **************
.subckt ofdm_receiver_discrete clk_frame clk_channel vec_bit_settings r_i r_q clk_data bits_rx clk_frame_rx vec_bit_settings_rx vec_qam_i vec_qam_q num_channels=1 num_cp=1 num_pilots=1 estimate=1 delay=1
xi0 r_i r_q clk_frame clk_channel vec_rm_cp_i vec_rm_cp_q vec_bit_settings ofdm_fft_serial_to_parallel_cp num_channels=num_channels num_cp=num_cp
xi1 vec_fft_i vec_fft_q vec_rm_cp_i vec_rm_cp_q clk_frame ofdm_remove_cyclicprefix num_channels=num_channels num_cp=num_cp
xi2 vec_fft_i vec_fft_q clk_frame vec_dqam_i vec_dqam_q ofdm_fft num_channels=num_channels
xi4 vec_z_i vec_z_q n0 clk_frame_rx vec_rx n3 n4 ofdm_detector num_channels=num_channels
xi5 vec_rx vec_bit_settings_rx clk_frame_rx clk_data bits_rx ofdm_receiver_parallel_to_serial num_channels=num_channels
xi3 clk_frame clk_frame_rx delay_fix delay=delay
xi10 vec_dqam_i vec_dqam_q n2 n1 vec_z_i vec_z_q clk_frame_rx n0 ofdm_onetap_equalizer num_channels=num_channels estimate=estimate
xi6 vec_bit_settings n0 delay_intvector8 delay=delay
xi8 vec_qam_q vec_pilot_q delay_vector8 delay=delay
xi9 vec_qam_i vec_pilot_i delay_vector8 delay=delay
xi11 n0 vec_bit_settings_rx delay_intvector8 delay=delay
xi7 vec_pilot_i vec_pilot_q vec_dqam_i vec_dqam_q clk_frame_rx n0 vec_h_mag vec_h_phase n2 n1 ofdm_channel_estimator num_channels=num_channels num_pilots=num_pilots estimate=estimate
.ends ofdm_receiver_discrete

************** Module ofdm_overall_system_dt **************
.subckt ofdm_overall_system_dt bits_tx clk_enable_tx vec_error_bits vec_total_bits vec_error_syms vec_total_syms clk_enable_rx
xi0 clk_frame clk_data clk_channel ofdm_clock_generator num_cp=num_cp_gl num_channels=num_channels_gl
xi3 clk_frame pilot_sel ofdm_pilot_selector num_pilots=num_pilots_gl
xi5 vec_bit_settings x_i x_q clk_enable_tx clk_data clk_frame clk_channel bits_tx vec_qam_i vec_qam_q ofdm_transmitter_discrete num_channels=num_channels_gl num_cp=num_cp_gl
xi7 n0 noise var=var_gl
xi8 n1 noise var=var_gl
xi9 y_i n0 r_i add2
xi10 y_q n1 r_q add2
xi12 bits_tx_delay bits_tx delay_sample_int delay=2*4*8*(num_channels_gl+num_cp_gl)
xi13 bits_tx_delay bits_rx clk_data clk_frame_rx n2 vec_total_bits vec_error_bits vec_error_syms vec_total_syms ofdm_ber num_channels=num_channels_gl
xi14 clk_enable_rx clk_frame_rx enable
xi1 pilot_vec_bit_settings int_vector8_constant elem0=1 elem1=1 elem3=1 elem2=1 elem4=1 elem5=1 elem6=1 elem7=1
xi6 x_i x_q y_i y_q ofdm_channel_cost259_model model=0
xi2 data_vec_bit_settings int_vector8_constant elem0=8 elem1=8 elem3=8 elem2=8 elem4=8 elem5=8 elem6=8 elem7=8
xi11 clk_frame clk_channel vec_bit_settings r_i r_q clk_data bits_rx clk_frame_rx n2 vec_qam_i vec_qam_q ofdm_receiver_discrete num_channels=num_channels_gl num_cp=num_cp_gl num_pilots=num_pilots_gl delay=4*8*(num_channels_gl+num_cp_gl)
xi4 pilot_sel vec_bit_settings pilot_vec_bit_settings data_vec_bit_settings mux2_intvectors vec_length=8
.ends ofdm_overall_system_dt


.end

