***** Hspice Netlist for Cell 'wb_synth_sd2' *****

************** Module accum_and_dump **************
.subckt accum_and_dump in out clk
.ends accum_and_dump

************** Module add2 **************
.subckt add2 in1 in2 out
.ends add2

************** Module and2 **************
.subckt and2 a b y
.ends and2

************** Module ch_pump **************
.subckt ch_pump in out ival=1
.ends ch_pump

************** Module constant **************
.subckt constant out consval=1
.ends constant

************** Module constant_interp **************
.subckt constant_interp out consval=1.0
.ends constant_interp

************** Module dffreset **************
.subckt dffreset d clk q qb r
.ends dffreset

************** Module dffset **************
.subckt dffset d clk q qb s
.ends dffset

************** Module divider_ideal **************
.subckt divider_ideal in div_val out
.ends divider_ideal

************** Module double_interp2bin **************
.subckt double_interp2bin in out
.ends double_interp2bin

************** Module gain **************
.subckt gain a y gain=1
.ends gain

************** Module inv **************
.subckt inv a y
.ends inv

************** Module latch1 **************
.subckt latch1 d latch q
.ends latch1

************** Module leadlagfilter **************
.subckt leadlagfilter in out fp=1 fz=1 gain=1
.ends leadlagfilter

************** Module mux2 **************
.subckt mux2 in0 in1 y sel
.ends mux2

************** Module rcfilter **************
.subckt rcfilter in out fo=1
.ends rcfilter

************** Module sd_modulator **************
.subckt sd_modulator in clk out order=1
.ends sd_modulator

************** Module step_in **************
.subckt step_in step vend=1 vstart=1 tstep=1
.ends step_in

************** Module sum_junct **************
.subckt sum_junct a y b
.ends sum_junct

************** Module vco **************
.subckt vco vctrl squareout sineout freq=1 kvco=1
.ends vco

************** Module vco_noise **************
.subckt vco_noise out noise_at_foff=-100 foff=1e6 kv=30e6
.ends vco_noise

************** Module xor2 **************
.subckt xor2 a b y
.ends xor2

************** Module wb_dac_en **************
.subckt wb_dac_en phi0 phi1 residue clk swap idac dacbits=6 idac_val=1e-3 mm=1.0 mmstddev=0.05 dwaen=1.0
.ends wb_dac_en

************** Module wb_delay **************
.subckt wb_delay in out delay=1.0
.ends wb_delay

************** Module wb_integrate_and_dump **************
.subckt wb_integrate_and_dump in clk out
.ends wb_integrate_and_dump

************** Module wb_tristate_gated_noise **************
.subckt wb_tristate_gated_noise mux_in out varpos=1 varneg=1
.ends wb_tristate_gated_noise

************** Module dff2 **************
.subckt dff2 d clk q qb
xi0 clk n0 inv
xi1 q qb inv
xi2 n1 n0 q latch1
xi3 d clk n1 latch1
.ends dff2

************** Module nand2 **************
.subckt nand2 a b y
xi0 a b n0 and2
xi1 n0 y inv
.ends nand2

************** Module wb_sample_and_hold **************
.subckt wb_sample_and_hold in s_and_h_clk out en_s_and_h=1
xi0 in s_and_h_clk n0 wb_integrate_and_dump
xi1 in n0 out n1 mux2
xi2 n1 constant consval=en_s_and_h
.ends wb_sample_and_hold

************** Module vco_with_noise **************
.subckt vco_with_noise squareout sineout noiseout vctrl fc=1.0 kv=1.0 foffset=1.0 noise_at_foffset=1.0
xi2 n1 vctrl n0 add2
xi3 n0 noiseout gain gain=kv
xi1 n1 vco_noise noise_at_foff=noise_at_foffset foff=foffset kv=kv
xi0 n0 squareout sineout vco freq=fc kvco=kv
.ends vco_with_noise

************** Module wb_phaseswap **************
.subckt wb_phaseswap div vco swap phi0 phi1 tdel_pfd_init=0.0 tdel_pfd_res=0.0
xi0 mux0 mux1 d0 swap mux2
xi1 mux1 mux0 d1 swap mux2
xi2 div vco mux0 n2 dff2
xi3 mux0 vco n1 n3 dff2
xi4 d0 vco phi0 n4 dff2
xi5 d1 vco n0 n5 dff2
xi6 n1 mux1 wb_delay delay=tdel_pfd_init
xi7 n0 phi1 wb_delay delay=tdel_pfd_res
.ends wb_phaseswap

************** Module wb_lfsr **************
.subckt wb_lfsr swap clk en_swap=1.0
xi23 n18 n22 n17 xor2
xi0 n17 clk swap n29 n7 dffset
xi12 n21 clk n2 n30 n7 dffset
xi21 n4 clk n5 n31 n7 dffset
xi24 n7 step_in vend=-1.0 vstart=1.0 tstep=60e-12
xi1 swap clk n19 n32 dff2
xi5 n0 clk n11 n33 dff2
xi6 n11 clk n10 n34 dff2
xi8 n9 clk n8 n35 dff2
xi10 n1 clk n12 n36 dff2
xi13 n2 clk n13 n37 dff2
xi14 n13 clk n3 n38 dff2
xi15 n3 clk n4 n39 dff2
xi16 n5 clk n15 n40 dff2
xi18 n14 clk n6 n41 dff2
xi19 n6 clk n16 n42 dff2
xi2 n18 clk n20 n43 n7 dffset
xi3 n19 clk n18 n44 dff2
xi4 n20 clk n0 n45 n7 dffset
xi7 n10 clk n9 n46 n7 dffset
xi9 n12 clk n21 n47 n7 dffset
xi11 n8 clk n1 n48 n7 dffset
xi17 n15 clk n14 n49 n7 dffset
xi20 n16 clk n23 n50 n7 dffset
xi22 n23 clk n28 n51 n7 dffset
xi25 n28 clk n27 n52 n7 dffset
xi26 n27 clk n26 n53 dff2
xi27 n26 clk n25 n54 n7 dffset
xi28 n25 clk n24 n55 n7 dffset
xi29 n24 clk n22 n56 dff2
.ends wb_lfsr

************** Module wb_pfddac **************
.subckt wb_pfddac div noise_en ichptot idac ref vco residue s_and_h_clk num_dac_bits=6 ichp=1e-3 mismatch_en=1.0 mmstddev=0.05 tdel_pfd_init=1 tdel_pfd_res=1 tdel_pfd_reset=1 en_swap=1.0 dwaen=1.0
xi0 vdd constant consval=1.0
xi1 vdd ref up n9 resdel dffreset
xi3 vdd phi0 pfd0 n0 res dffreset
xi4 vdd phi1 pfd1 n1 res dffreset
xi8 iup idac ichptot add2
xi12 n6 refb wb_lfsr en_swap=en_swap
xi9 iup_pre iup ch_pump ival=ichp
xi13 n0 n1 n8 nand2
xi15 n2 n3 gain gain=-1.0
xi16 n3 noise_en iup_pre sum_junct
xi5 div vco swap phi0 phi1 wb_phaseswap tdel_pfd_init=tdel_pfd_init tdel_pfd_res=tdel_pfd_res
xi6 res resdel wb_delay delay=tdel_pfd_reset
xi2 pfd0 pfd1 n4 and2
xi17 up n4 n5 and2
xi19 div divb inv
xi21 vdd n5 res n10 resdel dffreset
xi22 n6 n7 swap and2
xi18 n7 constant_interp consval=en_swap
xi14 n8 n2 double_interp2bin
xi10 up iup_pre double_interp2bin
xi23 up s_and_h_clk gain gain=-1.0
xi24 ref refb inv
xi11 pfd0 pfd1 residue refb swap idac wb_dac_en dacbits=num_dac_bits idac_val=ichp mm=mismatch_en mmstddev=mmstddev dwaen=dwaen
.ends wb_pfddac

************** Module wb_synth_sd2 **************
.subckt wb_synth_sd2 mod out sineout freqout ref dac_bits=7 accum_bits=20 mismatch_en=1 mismatch_stddev=0.05 tdel_pfd_init=0.0e-12 tdel_pfd_resid=5.0e-12 tdel_pfd_reset=3e-9 en_swap=1 div_start=71.3 div_end=71.3 div_step_time=8e-6 en_s_and_h=1
xi6 out div_val div divider_ideal
xi12 n1 ichptot itot add2
xi17 n0 vin rcfilter fo=2.5e6
xi15 n2 mod sd_in add2
xi8 n2 step_in vend=div_end vstart=div_start tstep=div_step_time
xi0 n3 constant consval=0.0
xi1 n3 ref n6 vco freq=50.0e6 kvco=1
xi7 n4 constant consval=0
xi9 freqout freqfilt trig_sig accum_and_dump
xi11 n4 trig_sig n7 vco freq=400e6 kvco=1
xi2 div pfdout ichptot idac ref out n5 shclk wb_pfddac num_dac_bits=dac_bits+1 ichp=5e-3 mismatch_en=mismatch_en mmstddev=mismatch_stddev tdel_pfd_init=tdel_pfd_init tdel_pfd_res=tdel_pfd_resid tdel_pfd_reset=tdel_pfd_reset en_swap=en_swap
xi13 itot shclk sh wb_sample_and_hold en_s_and_h=en_s_and_h
xi5 n5 constant consval=0.0
xi14 sd_in ref div_val sd_modulator order=2
xi3 pfdout n1 wb_tristate_gated_noise varpos=4.152e-21 varneg=4.152e-21
xi10 out sineout freqout vin vco_with_noise fc=3.565e9 kv=210e6 foffset=20e6 noise_at_foffset=-154
xi4 sh n0 leadlagfilter fp=2.8e6 fz=111e3 gain=1/(5.1e-9)
.ends wb_synth_sd2


.end

