verilog.log:  test.v test_lib.v test_lib.so
	ncverilog +ncams test.v -v test_lib.v +loadpli1=./test_lib.so:cpp_bootstrap
	@echo " "
	@echo "****************** VppSim run completed! *******************"
test_lib.so:  veriuser.o test_lib.o cppsim_classes.o
	g++ -m32 -fPIC -shared -o test_lib.so veriuser.o test_lib.o cppsim_classes.o
veriuser.o:  veriuser.c
	gcc -pipe -O -m32 -fPIC -c -o veriuser.o -I/afs/athena.mit.edu/dept/cadence/linux/IUS583USR6/tools/include -I/afs/athena.mit.edu/dept/cadence/linux/IUS583USR6/tools/inca/include ./veriuser.c
test_lib.o:  test_lib.cpp test_lib.h
	g++ -m32 -fPIC -c -o test_lib.o -O -I/afs/athena.mit.edu/dept/cadence/linux/IUS583USR6/tools/include test_lib.cpp
cppsim_classes.o:  /mit/6.22s/tools/vppsim/VppSimShared/CommonCode/cppsim_classes.cpp /mit/6.22s/tools/vppsim/VppSimShared/CommonCode/cppsim_classes.h
	g++ -m32 -fPIC -o cppsim_classes.o -c /mit/6.22s/tools/vppsim/VppSimShared/CommonCode/cppsim_classes.cpp
