cppsim_modules.so:  veriuser.o cppsim_modules.o cppsim_classes.o
	g++ -m32 -fPIC -shared -o cppsim_modules.so veriuser.o cppsim_modules.o cppsim_classes.o
	@echo " "
	@echo "****************** Compilation of VppSim modules completed! *******************"
	@echo " "
	@echo "Note: include this PLI code in Verilog(AMS) using option:"
	@echo "  -loadpli1 \$$VPPSIM/AMS/AMS_Examples/ams_test/cppsim_modules.so:cpp_bootstrap"
	@echo " "
	@echo "*********************************** Done! *************************************"
veriuser.o:  veriuser.c
	gcc -m32 -pipe -O -fPIC -c -o veriuser.o -I/opt/cadence/IUS55/tools/include -I/opt/cadence/IUS55/tools/inca/include ./veriuser.c
cppsim_modules.o:  cppsim_modules.cpp cppsim_modules.h
	g++ -m32 -fPIC -c -o cppsim_modules.o -O -I/opt/cadence/IUS55/tools/include cppsim_modules.cpp
cppsim_classes.o:  /u/VppSimShared/CommonCode/cppsim_classes.cpp /u/VppSimShared/CommonCode/cppsim_classes.h
	g++ -m32 -fPIC -o cppsim_classes.o -c /u/VppSimShared/CommonCode/cppsim_classes.cpp
